By Cam Nguyen, Meng Miao
This ebook offers the layout of ultra-wideband (UWB) impulse-based transmitter and receiver frontends, working in the 3.1-10.6 GHz frequency band, utilizing CMOS radio-frequency integrated-circuits (RFICs). CMOS RFICs are small, affordable, low energy units, greater suited to direct integration with electronic ICs in comparison to these utilizing III-V compound semiconductor units. CMOS RFICs are hence very appealing for RF structures and, actually, the important selection for advertisement instant markets.
The publication includes seven chapters. the 1st bankruptcy offers an advent to UWB know-how and descriptions its suitability for top solution sensing and high-rate, short-range ad-hoc networking and communications. the second one bankruptcy presents the fundamentals of CMOS RFICs wanted for the layout of the UWB RFIC transmitter and receiver offered during this booklet. It contains the layout basics, lumped and dispensed components for RFIC, format, post-layout simulation, and size. The 3rd bankruptcy discusses the fundamentals of UWB structures together with UWB merits and functions, indications, easy modulations, transmitter and receiver frontends, and antennas. The fourth bankruptcy addresses the layout of UWB transmitters together with an summary of simple elements, layout of pulse generator, BPSK modulator layout, and layout of a UWB tunable transmitter. bankruptcy five offers the layout of UWB receivers together with the layout of UWB low-noise amplifiers, correlators, and a UWB 1 receiver. bankruptcy 6
covers the layout of a UWB uniplanar antenna. eventually, a precis and end is given in bankruptcy 7.
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Extra resources for Design of CMOS RFIC Ultra-Wideband Impulse Transmitters and Receivers
2 Overview of Basic Components of UWB Impulse Transmitters 33 Fig. 5 Shunt-capacitor delay element Vout Vin M1 Vctrl M2 capacitor M2. The control voltage Vctrl adjusts the resistance of the shunt transistor M1, which connects the load capacitance M2 to the output of a logic stage. The tuning voltage Vctrl modulates the resistance of the shunt transistor M1, which is equivalent to changing the effective shunt capacitor value to the output of the inverter. Larger value of Vctrl decreases the resistance of the shunt transistor M1, so the effective shunt capacitance at the logic gate output is bigger, producing a larger time delay.
6 Block diagram of the CMOS UWB tunable monocycle pulse generator (a) (b) Vout Vin M1 Vout Vin M1 Vctrl M2 M2 Fig. 7 Circuit schematics of the tunable delay cell (a) and reference cell (b) discharging current to the capacitor M2. The only difference between the circuits of the tunable delay cell and reference cell is the gate voltage of the shunt transistor M1, which controls the charge current. For the tunable delay cell, variable control voltage Vctrl between 0 V and Vdd is applied to the gate of the transistor M1 to produce continuous delay variation.
When the tunable impulse signal is sent to the pulse-shaping circuit, a monocycle pulse signal with different durations is achieved at node D. 18-µm CMOS process . 18-µm CMOS Process Design Kit (PDK). 8-V supply voltage was used for the entire circuit. 40 3 UWB Impulse Transmitter Design Tunable delay Fig. 10 shows a photograph of the tunable CMOS monocycle pulse generator. The core of monocycle pulse generator only occupies an area of 240 µm Â 160 µm. The CMOS tunable monocycle pulse generator circuit and other accessory components were measured on-wafer in both time and frequency domains using a probe station, digitizing oscilloscope, and spectrum analyzer.